6525as?smic?16jan06 features general based on the arm ? sc100 ? securecore ? 32-bit risc processor two instruction sets ? arm high-performance 32-bit instruction set ?thumb ? high-code-density 16-bit instruction set von neumann load/store architecture ? single 32-bit data bus for instructions and data 3-stage pipeline architecture ? fetch, decode, and execute stages 8-bit, 16-bit, and 32-bit data types on-chip programmable syst em clock up to 50mhz very low power consumption ? industry leader in mips/watt ? low power idle and power down modes bond pad locations co nfirming to iso7816-2 esd protection to 6000v operating ranges: 1.62v to 5.5v, gsm/3g compliant, pc industry compatible, emv memory 512k bytes of rom program memory 384k bytes of eeprom, including 256 otp bytes ? typically more than 5 00,000 write/erase cycles at a temperature of 25 o c ? 10 years data retention eeprom erase only mode write eeprom with or without autoerase 24k bytes of ram (2k bytes shared with advx ? crypto processor) 32k bytes of rom dedicated to atmel?s crypto library peripherals one iso 7816 controller ? up to 625kbps at 5 mhz serial peripheral interface ( spi) controller (up to 20mhz) usb interface (5 endpoints) ? usb v2.0 full-speed (12mbps), suspend/resume modes supported ? 4 configurable endpoints in addition to endpoint ep0 ? dynamic pull-up attachment usb_ic (inter chip) 0.8e interface interface for external nand flash memory single wire interface (digital interface to rf front end chip) two 16-bit timers random number generator (rng) 2-level, 15-vector interrupt controller hardware des and triple des (dpa resistant) checksum accelerator crc 16/32 engine 32-bit cryptographic accelerator for public key operations ? rsa, dsa, ecc, diffie-hellman high performance hardware java card accelerator security dedicated hardware for protection against spa/dpa attacks protection against physical attack environmental protection systems voltage, frequency, light, and temperature protection systems 32-bit secure microcontrollers at91sc 512384rct summary note: this is a summary document. a complete document will be available under nda. for more information, please contact your local atmel sales office.
2 AT91SC512384RCT 6525as?smic?16jan06 secure memory management/access protection development tools hardware development support on the atv4-91sc voyager emulation platform software libraries an d application notes description the AT91SC512384RCT is a low power, high performance, 32-bit risc microcontro ller with rom program memory, eeprom data memory, and cryptographic accelerator, based on the arm sc100 advanced secure processor. this general purpose 32-bit processor offers high performance, very low power consumption, and additional features to help combat fraud. the AT91SC512384RCT f eatures 384k bytes of high performance eeprom (fast erase/write time, high endurance). the AT91SC512384RCT also features a us b full speed 2.0 port to allow very high speed transactions with a usb host terminal. usb interface requires the addition of an external 48mhz resonator. the AT91SC512384RCT features a spi (serial peripheral interface) port to provide either high speed interface with external terminal or to connect external nor flash memo ry. it also features an interface for nand flash memory. on top of the sc100s mpu, a real hardware firewall can be used to increase the overall security level of the application without intense software development. the cryptographic accelerator featured in the at91sc series is the advx ? , an n-bit multiplier-accumulator dedicated to performing fast encryption and authentication functions. advx is based on a custom 32-bit co-processor, thus enabling fast computation and low power operation. the advx in conjuction with controlling firmware running within the sc100 core, supports standard finite arithmetic functions (including rsa, dsa, dh and ecc) and gf(2n). unique hardware features significantly accelerate the execution of java card byte code by removing the common software bottlenecks encountered during the implementation of a java virtual machine. additional security features include power and frequency protection logic, logical scrambling on program data and addresses, power analysis countermeasures, and memory access controlled by a supervisor mode. pin configuration the AT91SC512384RCT pinout configuration confirms to the iso7816-2 interface. note: by convention, the rst pin corresponds to the rst signal of the iso7816-3 protocol, both are active low.) gnd ground (reference voltage) we flash interface (write enable) vcc power supply input ale flash interface (address latch enable) iso i/o0 input or output for serial data (iso7816 cle flash interface (command latch enable) iso clk clock signal input to external clock operating circuit ce flash interface (chip enable) iso rst reset signal input, a low state stops the arm core re flash interface (read enable) c6 swp dedicated pin io0 flash interface io0 usb d+ usb d+ io1 flash interface io1 usb d- usb d- io2 flash interface io2 usb xin usb xin io3 flash interface io3
3 AT91SC512384RCT 6525as?smic?16jan06 architectural overview the sc100 is a 3 stage pipeline, 32-bit risc processor. it us es a von neumann load/store architecture, this architecture is characterized by a single data and address bus for instruction data. the sc100 processor employs a unique architectural strategy known as thumb ? , a super reduced instruction set that is ideally suited for high volume applications with memory restrictions, and applications where code density is an important factor. essentially, the sc100 processor has two instruction sets: the standard arm instruction set using 32-bit instructions and offering maximum performance the thumb instruction set using 16-bit instructions and offering maximum code density both instruction sets operate on 8-bit, 16-bit and 32-bit data types. the thumb?s 16-bit instruction length allows it to achieve al most twice the density of standard arm code, whilst retaining most of the arm performance advantage over a traditional 16-bit processor using 16-bit registers. this is possible because the 16-bit thumb instructions operate on the same 32-bit register set as the 32-bit arm instruction set. thumb code can be up to 35% smaller than the equivalent arm code, whilst providing 160% of the performance of an equivalent arm processor connected to a 16-bit memory system. figure 1 shows the block diagram of the AT91SC512384RCT device. usb xout usb xout ss /io4 spi slave select/flash interface io4 wp flash interface (write protect) sck/io5 spi clock/flash interface io5 mosi/io6 spi master output-slave input/flash interface io6 miso/io7 spi master output-slave input/flash interface io7
4 AT91SC512384RCT 6525as?smic?16jan06 figure 1. AT91SC512384RCT block diagram pipeline rom program memory thumb instruction decompressor advx crypto- accelerator iso 7816 i/o port 0 timer eeprom user memory otp secure control firewall i/o0 des/3des 32 on-chip security (spa, dpa, ...) reset circuit rst iso 7816 controller crc16&32 engine sc100? core 32 32 ram java accelerator rng mpu 32 32 8/16/32 8/16/32 spi controller i/o0 usb swp smc i/o0 flash controller io 0 io 1 io 2 io 3 ss / io 4 sck / io 5 mosi / io 6 miso / io 7 cle ale ce wp we re c6 d+ d- xin xout clk gnd vcc miso mosi ss sck rd wr addr data
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